2009 December | Computers

Ecc Registered

December 30th, 2009 admin No comments

Ecc Registered

Components of Solid State Drive (SSD)

Flash Memory:

The solid-state flash memory is used as a non-volatile memory to store data permanent. Two types of Main flashes are there, NOR and NAND. Depend upon the usage, any of either use as a permanent storage here. The above two have it’s own advantages and limitations also. The interface provided for reading and writing also differs. Basically NOR has long erase and write times. NAND has lower cost.

Flash Memory Controller:

Approximately three percent of the overall SSD memory array is reserved as a "spare area". Approximately three to six bytes in the spare area are reserved for error detection and correction algorithms, while the remainder of the spare area is used for remapping bad blocks. Without a SSD flash memory controller the algorithms that handle these functions would be executed by the general purpose CPU. However, SSD controllers are available that will perform these functions in hardware. This reduces the CPU load on the device, which has the effect of speed up the performance. In addition, the advent of Multi-Level Cell (MLC) NAND flash Technology requires even more rigorous error detection algorithms due to the increased chance of an error occurring. A Flash controller is perhaps the only reasonable way of performing this task.

This Flash Controllers can implement read and write caching and transfer data to and from the flash chip independently of the general purpose CPU. This increases the overall throughput and can again reduce the load on the system. Integrated NAND controllers are growing in popularity as mobile processor vendors, such as ‘Freescale’ and Texas Instruments, build NAND controllers directly into their processors. The advantages of this approach are that the design can be kept small and the costs can be minimized. The disadvantage is the inevitable delay between a new NAND flash technology appearing and the release of an integrated processor that supports it.

At a higher level, an intelligent block device driver, such as flashFX Pro from Data light, or a flash file system often utilizes the NAND controller driver. Some important functions of this software are:

Reducing the integration time for developers of embedded applications
Handling bad blocks present on the NAND flash chip
Providing small block emulation, which is required due to the relatively large "erase blocks" present on NAND flash
Mitigating the effects of wear on the NAND flash through the application of wear leveling algorithms that spread writes and erases over a wider area
Providing a file system interface that allows you to interact with the flash chip at the file level

FIFO:

FIFO is an algorithm for First In, First Out, an abstraction in ways of organizing and manipulation of data relative to time and prioritization. This expression describes the principle of what comes in first is handled first, what comes in next waits until the first is finished. In here this FIFO and its control is used as intermediate between RAM controller and Flash controller. There is an algorithm used here is called Disk Scheduling Algorithm.

Disk Scheduling Algorithm:

In most systems there are many process that are running simultaneously. Often, many processes request I/O operations from/to the hard drive. The algorithm used to select which request is going to be satisfied first is called "disk scheduling algorithm."

There are two objectives for any disk-scheduling algorithm:
1. Minimize the throughput - the average number of requests satisfied per time unit.
2. Maximize the response time - the average time that a request must wait before it is satisfied.

ECC:

Error detection and correction has great practical importance in maintaining information integrity across channels and less-than-reliable storage media. Here in SSD, an error-correcting code (ECC) or forward error correction (FEC) code is a code in which each data signal conforms to specific rules of construction so that departures from this construction in the received signal can generally be automatically detected and corrected. Here it’s used in RAM and in data transmission. The basic idea is for the transmitter to apply one or more of the error detecting codes; then the receiver uses those codes to narrow down exactly where in the message the error (if any) was. If there was a single bit error in transmission, the decoder uses those error-detecting codes to narrow down the error to a single bit (1 or 0), then fix that error by flipping that bit. Some schemes are there to use here, they are repetition schemes, parity schemes, cyclic redundancy checks, Hamming distance based checks etc.,

RAM:

RAM (random access memory) is the place in a computer where the operating system, application programs, and data in current use are kept so that they can be quickly reached by the computer's processor. RAM is much faster to read from and write to than the other kinds of storage in a computer, the hard disk, floppy disk, and CD-ROM. However, the data in RAM stays there only as long as the computer is running. Whenever the user turns the computer off, RAM loses its data. When user turn computer on again, your operating system and other files are once again loaded into RAM, usually from the hard disk.

RAM Controller:

The RAM controller used here to access the data from RAM according to the instruction by Processor. When the processor or CPU gets the next instruction it is to perform, the instruction contains the address of RAM location from which data is to be read (brought to the processor for further processing). This address is sent to the RAM controller. The RAM controller organizes the request and sends it down the appropriate address lines so that transistors along the lines open up the cells so that each capacitor of the RAM value can be read. A capacitor with a charge over a certain voltage level represents the binary value of 1 and a capacitor with less than that charge represents a 0. For dynamic RAM, before a capacitor is read, it must be power-refreshed to ensure that the value read is valid. Depending on the type of RAM, the entire line of data may be read that the specific address happens to be located at or, in some RAM types, a unit of data called a page is read. The data that is read is transmitted along the data lines to the processor's nearby data buffer known as level-1 cache and another copy may be held in level-2 cache.

Flash Control Register:

Flash control registers in solid-state disks controls write protection of static memory devices.

Processor:

A processor is the logic circuitry that responds to and processes the basic instructions that drive a system like computer. The term processor has generally replaced the term central processing unit (CPU) in computer. In a computer's assembler language, each language statement generally corresponds to a single processor instruction. In high-level languages, a language statement generally results (after program compilation) in multiple processor instructions. In assembler language, a macroinstruction is one that, during processing by the assembler program, expands to become multiple instructions (based on a previously coded macro definition). The SSD can be used in RISC processor (such as SPARC, MIPS and PA) also. Most of the pocket PC’s has MIPS processor running at 166mhz with 64bit addressing with SSD.

About the Author

Design Engineer, Tata Elxsi Limited, ITPB Road, Whitefield, Bangalore - 560048, Karnataka, India - Mail: mskumar@tataelxsi.co.in / mskumar86@myway.com - Ph: +91 9916516728

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